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As a member of the mixed signal team, the candidate will work with senior circuit designers in the design, validation and characterization of mixed signal and analog IP blocks for SOC. The IPs include PLL, DLL, SERDES, high speed IO and data converters, etc. for sub-14nm technologies. The candidate will have exposure to a broad range of circuit and technologies. In addition, the candidate will work with engineers of various disciplines in the development and enhancement of analog/digital design methodology.
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