DFT and Design Engineer Intern at Ambarella
Santa Clara, CA, US

Position Responsibilities:

  • Logic Design to support DFT features
  • Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC
  • Verification of DFT Logic and analysis of fault coverage
  • Timing analysis for DFT Modes
     

Minimum Requirements:

  • MSEE in Electrical / Computer Engineering
  • Knowledge of DFT fundamentals
  • Knowledge of Logic design  & Static timing analysis
  • Knowledge of Verilog and any scripting language