ASIC Design Engineer at Ambarella
Santa Clara, CA, US

Position Responsibilities:

  • Developing micro-architecture specifications for a next generation Computer Vision processor.
  • Designing and implementing video compression logic, image processing logic, and computer vision processors in Verilog and SystemVerilog.
  • Design integration, logic synthesize, and design optimization for timing, area and power.
  • Developing unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using system verilog, UVM, C++, and perl scripts.
  • Developing test plan, random and directed test cases, performing logic verification, and functional coverage analysis.
  • Developing front-end methodologies and tool flows.
  • Participating in chip bring-up and testing.

 

Requirements:

  • Master’s degree in Electrical Engineering with 3-7 years of experience.
  • Very Good understanding of Computer architecture, Microprocessor, Digital electronics, VLSI/ASIC design, and Logic design.
  • Good knowledge and experience in using hardware description languages, like, Verilog/SystemVerilog.
  • Ability to program in scripting languages, like Perl.
  • Knowledge of design verification, and functional coverage.
  • Strong communication skills and a good team player.
  • Knowledge is logic synthesis and timing closer are must, and some experience is a plus.
  • Knowledge and/or experience in the areas of Image/Video processing, computer vision, machine learning are plus.