Sr, HW Dev Engr at Infinera Corporation
Shanghai, CN

Your Key Responsibilities Would Include:

As a member of FPGA design team inside hardware development team, qualified candidate shall design, modify, and test FPGA/CPLD for new card development.

  • Participate in system requirement and architecture review.
  • Preparation and review FPGA design specification.
  • FPGA implementation including chip selection, pin definition, coding, simulation, synthesis and place & route.
  • Work with other teams to bring up card.
  • Make test plan and test strategy. Ensure effective testing and high quality product delivery.



Education & Experience Necessary For Success:

  • Bachelor/Master of Science (Electrical Engineering or relevant majors) with 3+ years' experience in FPGA/ASIC design.
  • Complete understanding of the FPGA/ASIC design flow.
  • Very good HDL coding and modeling experience.
  • Good Experience with simulation and verification on board.
  • Familiar with PLD verdors' tool and product is a plus.
  • Design background in OTN or packet based telecommunication equipment is a plus.
  • Innovative thinking and team working spirit.
  • Be initiative, ability to analyze and learn.
  • High team and result orientation are required.
  • Excellent interpersonal, written and verbal communications skills in Mandarin and English.