Verification Engineer at Ambarella
HsinChu, TW
** Develop Testbenches for DSP logic blocks, processor cores, coprocessor cores and other digital logic devices in SystemVerilog, C and C++.
** Write measurable verification plans for the above mentioned DUT-s for pre-silicon chip validation at block or full chip level.
** Write and debug tests for the above-mentioned DUT-s using SystemVerilog, Perl, Assembly, C, C++ and possibly other languages.
** Write reusable constraint random test generators with automated checking.
** Write coverage monitors to evaluate the coverage of the DUT-s.
** Apply static or dynamic assertion based verification where it has best ROI.
** Create sub-system and system level tests pre-and-post silicon.