Verification Engineer at Ambarella
Santa Clara, CA, US

Responsibilities:

  • Develop test benches in UVM, SystemVerilog, Verilog, C, C++ and other languages.
  • Write test plans for digital signal processing logic blocks, control logic blocks, general-purpose processor cores and other digital logic devices.
  • Write and debug tests for a complex media processor in UVM, SystemVerilog, Verilog, C, C++, Perl, Python and other languages.
  • Develop verification tools.
  • Perform coverage analysis using CAD tools.
  • Perform system-level verification of Ambarella’s Video Input block as well as other blocks.
  • Perform Block Verification of Ambarella’s very complex CABAC compression block.

Requirements:

  • You must possess a MSEE/CE degree.
  • Knowledge of video compression and decompression algorithms.
  • Knowledge of different types of memories and memory subsystems; e.g., DDR4, LPDDR3, LPDDR4.