ASIC Design Engineer at Ambarella
Santa Clara, CA, US

Position Responsibilities:

  • Developing micro-architecture spec and implement design blocks in Verilog
  • Design RTL to interface/control mixed-signal blocks
  • Design integration, logic synthesis and design optimization for area, timing and power
  • Developing front-end methodologies and tool flows
  • Participating in chip bring-up and testing

 

Minimum Requirements:

  • MSEE in Electrical / Computer Engineering with 0-2 years of experience
  • Good understanding of digital electronics, VLSI/ASIC design, and logic design
  • Knowledge and experience in using hardware description languages like Verilog/System Verilog
  • Knowledge of logic synthesis and timing closure
  • Knowledge/Experience of handling logic with multiple clock domains
  • Knowledge of Perl and/or Python